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hw.h

/* 
* This is part of the source for i855crt driver
* copyright(c) Merello Andrea 2004
* <andreamrl@tiscali.it>
*
* this is released under the terms of GPL (General Public Licence)
*
* some parts of this driver are taken/based  from/on the 'i810switch' driver
* many thanks to the original author.
*
* some parts of this driver are taken/based  from/on the 855GM-fb driver
* many thanks to the original author.
* 
* plase note that this driver is still experimental
*
* feedbacks are VERY appreciated
*/

/* registers */

/*
* some comes from the i815 datasheet, some from i810switch, some from i810 X driver, 
* some from the 855GM fb driver, and some are even guessed or comes from docs wrote
* by people who guessed them... 
*/

/*
#define VGACNTRL        0x71400
#define VGA_DISABLE                 (1 << 31)

#define PWR_CLKC        0x06014

#define I830_ADPA       0x61100
#define DSPACTRL        0x70180
#define DSPBCTRL        0x71180

#define DCLK_0D 0x6000
#define DCLK_1D 0x6004
#define DCLK_0DS 0x6010
*/
#define BLANK_RESERVED_MASK ((1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<28)|(1<<29)|(1<<30)|(1<<31))
#define TOTAL_RESERVED_MASK ((1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<28)|(1<<29)|(1<<30)|(1<<31))
#define SYNC_RESERVED_MASK ((1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<28)|(1<<29)|(1<<30)|(1<<31))
#define HTOTAL_A    0x60000
#define HBLANK_A    0x60004
#define HSYNC_A     0x60008
#define VTOTAL_A    0x6000c
#define VBLANK_A    0x60010
#define VSYNC_A     0x60014
#define PIPEASRC    0x6001c
#define BCLRPAT_A   0x60020
#define PIPEARESERVED_MASK ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)

#define HTOTAL_B    0x61000
#define HBLANK_B    0x61004
#define HSYNC_B     0x61008
#define VTOTAL_B    0x6100c
#define VBLANK_B    0x61010
#define VSYNC_B     0x61014
#define PIPEBSRC    0x6101c
#define BCLRPAT_B   0x61020

#define DPLL_A      0x06014
//#define DPLL_B      0x06018
#define DPLL_VCO_ENABLE             (1 << 31)
#define DPLL_2X_CLOCK_ENABLE        (1 << 30)
#define DPLL_SYNCLOCK_ENABLE        (1 << 29)
#define DPLL_VGA_MODE_DISABLE       (1 << 28)
#define DPLL_P2_MASK                1
#define DPLL_P2_SHIFT               23
#define DPLL_P1_FORCE_DIV2          (1 << 21)
#define DPLL_P1_MASK                0x1f
#define DPLL_P1_SHIFT               16
#define DPLL_REFERENCE_SELECT_MASK  (0x3 << 13)
#define DPLL_REFERENCE_DEFAULT            (0x0 << 13)
#define DPLL_REFERENCE_TVCLK        (0x2 << 13)
#define DPLL_RATE_SELECT_MASK       (1 << 8)
#define DPLL_RATE_SELECT_FP0        (0 << 8)
#define DPLL_RATE_SELECT_FP1        (1 << 8)

#define FPA0                  0x06040
#define FPA1                  0x06044
/*#define FPB0                0x06048
#define FPB1                  0x0604c*/
#define FP_DIVISOR_MASK             0x3f
#define FP_N_DIVISOR_SHIFT          16
#define FP_M1_DIVISOR_SHIFT         8
#define FP_M2_DIVISOR_SHIFT         0
/* Clock values are in units of kHz */
#define PLL_REFCLK            48000
#define MIN_M                 108
#define MAX_M                 140
#define MIN_M1                18
#define MAX_M1                26
#define MIN_M2                6
#define MAX_M2                16
#define MIN_P                 4
#define MAX_P                 128
#define MIN_P1                0
#define MAX_P1                31
#define MIN_N                 3
#define MAX_N                 16
#define MIN_VCO_FREQ          930000
#define MAX_VCO_FREQ          1400000
#define MIN_CLOCK       25000
#define MAX_CLOCK       350000
#define P_TRANSITION_CLOCK    165000
#define CALC_VCLOCK(m1, m2, n, p1, p2) \
 ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / (((p1) + 2) * (1 << (p2 + 1))))
#define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p))

#define ADPA             0x61100
#define DVOA             0x61120
#define DVOB             0x61140
#define DVOC             0x61160

#define DVOA_SRCDIM      0x61124
#define DVOB_SRCDIM      0x61144
#define DVOC_SRCDIM      0x61164

#define LCD             0x61180
#define PORT_ENABLE                 (1 << 31)
#define PIPEACONF 0x70008


#define PIPEBCONF 0x71008
#define PIPE_ENABLE                 (1 << 31)

#define DSPACNTR         0x70180
#define DSPBCNTR         0x71180
//#define DSPCURRCNTR   0x70080
//#define DSPCURRBASE   0x70084
//#define DSPCURRPOS 0x70088
#define DSPCNTR_RESERVED_MASK ((1<<23) | (1<<21)| (1<<19) | (1<<16) | (1<<17) | 0x7fff)
#define DSPCNTR_PIPE    (1<<24)
#define DSPBASE_RESERVED_MASK ((1<<31)|(1<<30)|(1<<29) | (255))
#define DSPABASE         0x70184
#define DSPASTRIDE       0x70188
/* bits 14-12 in DAC register are unknow and are trated as reserved*/
#define DAC_RESERVED_MASK ((1<<16)|(1<<17)|(1<<18)|(1<<19)|(1<<20)|(1<<21)|(1<<22)|(1<<23)|(1<<24)|(1<<25)|(1<<26)|(1<<27)|(1<<28)|(1<<29)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<0)|(1<<1)|(1<<2));

#define DSPBBASE         0x71184

#define DSPBSTRIDE       0x71188

#define CURSOR_CONTROL        0x70080
#define CURSOR_ENABLE               (1 << 31)

/*
#define CURSOR_STRIDE_MASK          (0x3 << 28)
#define CURSOR_STRIDE_256           (0x0 << 28)
#define CURSOR_STRIDE_512           (0x1 << 28)
#define CURSOR_STRIDE_1K            (0x2 << 28)
#define CURSOR_STRIDE_2K            (0x3 << 28)
#define CURSOR_FORMAT_MASK          (0x7 << 24)
#define CURSOR_FORMAT_2C            (0x0 << 24)
#define CURSOR_FORMAT_3C            (0x1 << 24)
#define CURSOR_FORMAT_4C            (0x2 << 24)
#define CURSOR_FORMAT_ARGB          (0x4 << 24)
#define CURSOR_FORMAT_XRGB          (0x5 << 24)*/

/* Mobile HW cursor (and i810) */
#define CURSOR_A_CONTROL      CURSOR_CONTROL
#define CURSOR_B_CONTROL      0x700c0
#define CURSOR_MODE_MASK            0x27
#define CURSOR_MODE_DISABLE         0
#define CURSOR_MODE_64_3C           0x04
#define CURSOR_MODE_64_4C_AX        0x05
#define CURSOR_MODE_64_4C           0x06
#define CURSOR_MODE_64_32B_AX       0x07
#define CURSOR_MODE_64_ARGB_AX            0x27
#define CURSOR_PIPE_SELECT_SHIFT    28
#define CURSOR_GAMMA_ENABLE   (1 << 26)
#define CURSOR_MEM_TYPE_LOCAL       (1 << 25)
//#define CURSOR_MODE            0x27
/* All platforms (desktop has no pipe B) */
#define CURSOR_A_BASEADDR     0x70084
#define CURSOR_B_BASEADDR     0x700c4
#define CURSOR_BASE_MASK            0xffffff00
#define CURSOR_PIPE_SELECT    (1 << 28)
/*
#define MCURSOR_GAMMA_ENABLE   (1 << 26)
#define MCURSOR_MEM_TYPE_LOCAL (1 << 25)*/
#define CURSOR_A_POSITION     0x70088
#define CURSOR_B_POSITION     0x700c8
#define CURSOR_POS_SIGN             (1 << 15)
#define CURSOR_POS_MASK             0x7ff
#define CURSOR_X_SHIFT              0
#define CURSOR_Y_SHIFT              16

#define CURSOR_A_PALETTE0     0x70090
#define CURSOR_A_PALETTE1     0x70094
#define CURSOR_A_PALETTE2     0x70098
#define CURSOR_A_PALETTE3     0x7009c
#define CURSOR_B_PALETTE0     0x700d0
#define CURSOR_B_PALETTE1     0x700d4
#define CURSOR_B_PALETTE2     0x700d8
#define CURSOR_B_PALETTE3     0x700dc
#define CURSOR_PALETTE_MASK               0xffffff

#define OV0CONFRO 0x30164
#define OV0CONFWR 0x64
#define OV0ADDR 0x30000
#define OV0ADDRMASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<17)|(1<<18)|(1<<19)|(1<<20)|(1<<21)|(1<<22)|(1<<23)|(1<<24)|(1<<25)|(1<<26)|(1<<27)|(1<<28))
#define OVERLAY_PIPE_SELECT   (1<<18)
#define OVERLAYMMIOBASE       0x30100     

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